FailSafe(TM) devices provide an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous operation is achieved using a DCXO that serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique FailSafe IP block eliminates sudden output phase changes, aka. 'phase bumps', which usually occur in conventional clock distribution devices as the user switches between two asynchronous reference clock sources.

Field Programmable Zero Delay Buffer is a high-performance clock distribution device that can be customized for a wide range of applications. The device is implemented on Cypress's proprietary non-volatile technology. It is fully programmable via volume or prototype programmers. The device enables the user to define an application-specific clock distribution device with customized input and output dividers, feedback topology (internal/external), output inversions and output drive strengths.