FPGA processor board
EDT
The PCIe8 LX has a programmable FPGA (Xilinx Virtex 5 LXT) and synchronous memory of 8 MB SRAM and up to 2 GB 200-pin SODIMM DDR2 DRAM.
The board also has four independent programmable PLL clock generators, which can be set to select frequencies from 1 to 45 MHz with less than +/- 50 ppm error.
An EDT Bridge can be used to link two main boards together.
Requirements
System must have a PCI Express bus (8 or 16 lanes) that is not dedicated to display use only. See bandwidth requirements.
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