Structured ASIC
GigOptix
* Pre-validated mixed signal PHYs and PLLSUp to 500 signal I/O's configurable in metal
* Fully configurable logic and memory structures
* XPath conversion to Standard CellAvailable for 0.35μ, 0.25μ, 0.18μ and 0.13μ designs
Ideal for:
* Risk mitigation with complex mixed-signal IP's, such as USB and PCI Express
* Rapid implementation and fabrication of complex designs
* Low NRE and low to mid-volume designs
* Cost reduction of expensive FPGAs
* Fully configurable logic and memory structures
* XPath conversion to Standard CellAvailable for 0.35μ, 0.25μ, 0.18μ and 0.13μ designs
Ideal for:
* Risk mitigation with complex mixed-signal IP's, such as USB and PCI Express
* Rapid implementation and fabrication of complex designs
* Low NRE and low to mid-volume designs
* Cost reduction of expensive FPGAs
-
zoom








