Imagine designing your clock nets without using an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts! The answer is Lattice's revolutionary ispClock5600A family for complex clock nets and ispClock5300S family for simple clock nets. Lattice's ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements - all while meeting stringent skew and jitter standards!