RISC microprocessor
PMC Sierra
High-performance 64-bit integer unit.
High-throughput fully pipelined 64-bit floating point unit (IEEE 754).
High performance SysAD interface:
32-bit or 64-bit multiplexed system address/data bus for optimum price/performance.
Available with 32-bit or 64-bit external bus interface
Supports fractional clock ratios.
IEEE 1149.1 JTAG boundary scan.
Integrated primary caches:
32 KB instruction - 2-way set associative.
32 KB data - 2-way set associative.
Virtually indexed, physically tagged.
Write-back and write-through on per-page basis.
Pipeline restart on first double word for data cache misses.
64-bit MIPS instruction set architecture:
Floating point multiply-add instruction increases performance in signal processing and graphics applications.
Conditional moves to reduce branch frequency.
Index address modes (register + register).
Integrated memory management:
Fully associative joint TLB (shared by I and D transistors).
48 dual entries map 96 pages.
Variable page size (4 KB to 16 MB).
Embedded application enhancements:
Specialized DSP integer Multiply-Accumulate instructions (MAD/MADU) and 3 operand Multiply instruction (MUL).
Instruction and Data cache locking by set.
Optional dedicated exception vector for interrupts.
