Digital signal processor (DSP)
Tensilica
Processors for the SOC Dataplane
Xtensa LX4
In today's complex SOC designs, processors can be found in many places throughout the chip to add programmability for design flexibility. While most processors do a good job with control functions, they often fail miserably at the complex dataplane processing tasks. That's why designers often turn to RTL blocks for the complex "heavy lifting" SOC tasks. The problem with those RTL blocks is that they take too long to design, take even longer to verify, and are not programmable.
What's needed are processors that can be customized for the task at hand with just the functions, registers and datapath required. In order to provide enough data bandwidth to and from other system blocks, the processor must provide direct connectivity with arbitrary widths and predictable latency without using the system bus.
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