Backplane transceiver
Vitesse Semiconductor
parallel-to-serial and serial-to-parallel
transceiver chip designed for use in high
bandwidth data transmission between
busses, backplanes and other subsystems.
Each channel's transmitter section contains parallel 8-bit or
10-bit input circuitry, an 8B/10B encoder, serializer and a pair
of serial PECL output drivers and additional control inputs.
Each channel's receiver section contains a pair of PECL
inputs, clock and data recovery circuitry, a deserializer, an
8B/10B decoder, elastic buffers, 8-bit or 10-bit output drivers
and additional control outputs. Each transmitter may be
supplied 8-bit data which will be encoded into 10-bit
characters for transmission, or may be supplied preencoded
10-bit data in which case the internal encoder is
bypassed. The four channels may operate independently
or in a synchronized mode transferring data that is wordaligned
across 16 or 32 data inputs.
