Link-layer framer / mapper
Vitesse Semiconductor

The Vitesse virtual concatenation (VC) mappers not only dramatically lower equipment costs, but also make SONET/SDH systems far more flexible and efficient in bandwidth allocation.

Key Features
* Support for the Link Capacity Adjustment Scheme (LCAS) protocol with hitless adds, removes, and fault isolation
* External DDR SDRAM for diverse routing applications
* Flexible payload processing for generic framing procedure (GFP) that supports several interfacing formats, including Ethernet frames
* Support for HDLC-like framing: PoS - RFC2615, LAPS - X.85, and X.86
* Extensive performance monitoring features
* Generic 16-bit microprocessor interface
* System Packet Interface Level 4 (SPI-4), Phase 2

Basic Mapping (VSC9125 and VSC9128)
* Dual 4 × 2.5 Gbps serial STS-48/STM-16-like backplane interfaces with TSI performance monitoring (work/protect)
* Complete STS-192/VC-4-64 section, line, and path termination and generation
* Full access to SONET/SDH section and line overhead bytes through dedicated ports
* Channelized payload mapping into STS-1; TU-3/VC-3; STS-3c/VC-4, STS-12c/VC-4-4c, or STS-48c/VC-4-16c; STS-192c/VC-4-64c; or virtual groups composed of STS-1 SPEs, TU-3/VC-3s, or STS-3c/VC-4s
* Low-Order Concatenation (VSC9135 and VSC9138)
* Choice of any 24 STS-1s or VC-3s to process for low-order tributaries
* High-order POH ports for external sourcing or processing
* Support for contiguously concatenated transport channels: STS-3c/AU4, STS-12c/AU4-4c, STS-24c/AU-4-8c, STS-48c/AU-4-16c, and STS-192c/AU4-64c
* PRBS generation and detection for testing data channels
* Optional GFP header insertion and removal