Complex / simple programmable logic device (CPLD, SPLD)
3.3 V | XC9500XL
Xilinx
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9500XL device supports in-system programming
(ISP) and the full IEEE Std 1149.1 (JTAG) boundary-
scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx® Virtex®,
Spartan®-XL and XC4000XL FPGA families, allowing system
designers to partition logic optimally between fast interface
circuitry and high-density general purpose logic. As
shown in Table 1, logic density of the XC9500XL devices
ranges from 800 to 6400 usable gates with 36 to 288 registers,
respectively. Multiple package options and associated
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