The BERTScope Clock Recovery CR Series advanced architecture measures and displays the PLL frequency response from 100 kHz to 12 MHz; the highest loop bandwidth available for jitter testing on the market today. The first clock recovery instruments to allow full control of parameters including loop bandwidth, peaking/damping, and roll off.
Data Rate Range up to 28.6 Gb/s
Independent control, measurement, and display of phase lock loop (PLL) BW, JTF (jitter transfer function) and peaking.
Clock Recovery Input Equalization
Edge Density Measurement
Jitter Spectral Analysis and Frequency Gated Integrated Jitter Measurements
Optional 24 MHz PLL BW
Extensive set of subrate (recovered) clock outputs.
Continuous data rate coverage for next generation I/Os including PCIe 3.0, 10GBASE-KR, 16xFC, 25 & 28G CEI and 100GBASE-LR-4 & ER-4.
Provides accurate "Golden PLL" response for transmitter jitter compliance testing and stressed receiver sensitivity test calibration. Provides full flexibility for device characterization.
Enables clock recovery on high ISI signals without impacting the data stream under test. Recovered clock enables other analysis including "clean eye", application of FIR filtering to signal, and BER testing.
Allows instant determination of the mark density of the signal under test.
Provides 200 Hz to 90 MHz display of jitter vs frequency with cursor based measurements of jitter peaks' amplitude and frequency. Frequency gated integrated jitter measurements PCIe 2.0 compliance testing.
Meets the JTF bandwidth requirements of USB 3.0, 6 G SATA, and PCIe-Gen 3.
Frequently needed for device reference clocks.