Analysis software PathFinder-SC

simulationdesignplanning

Ansys PathFinder-SC is a high-capacity solution to help you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). Full-Chip Layout Level ESD Signoff Solution for SOC IP Ansys PathFinder-SC identifies and isolates the root causes of design issues that can cause chip failure from charged-device model (CDM), human body model (HBM), or other ESD events. It’s high-capacity, cloud-native architecture can enlist thousands of compute cores for fast full-chip turnaround. PathFinder-SC is certified by major foundries for resistance and current density checks for ESD signoff. Integrated with Ansys RedHawk-SC™ and Ansys Totem™ Outputs Chip ESD Compact Model (CECM) Quick Specs PathFinder-SC’s integrated data modeling, extraction and transient simulation engine is an end-to end solution for ESD verification. The single-pass use model reads industry-standard design formats, sets up ESD rules, extracts the RCs for the power network, and performs ESD simulations to analyze root causes and provide fix and optimization feedback, all within a single tool. CDM & HBM Coverage P2P Resistance Checks Current Density and IR Checks GDS and Digital Flow Support Cloud-native Architecture Analyze Multiple Domains in a Single Run Handles Snap-back ESD More Than 100 Million Instance Capacity Layout GUI for Debug Compact ESD Model for IP