Development platform software package VectorBlox™ Accelerator SDK

converterprogrammingdata conversion

Overview

• The VectorBlox™ Accelerator SDK provides a software-based AI/ML inference engine optimized for Microchip PolarFire® and PolarFire SoC FPGAs, focusing on power-efficient Convolutional Neural Network (CNN) inference and video pipelines.
• Key capabilities include software deployment without reprogramming the FPGA, support for sparse networks (structured and unstructured compression), and configurable performance vs. power trade-offs.

Compression and Memory Efficiency
The SDK (VectorBlox 3.x) reduces memory usage and data movement through both structured and unstructured compression techniques. Structured compression targets regularly laid-out data (weights, activations, feature maps) enabling deterministic, low-overhead decompression in hardware. Unstructured compression stores only nonzero values with indices to support sparse and irregular data patterns, allowing larger models or higher-resolution data within fixed memory/bandwidth constraints on edge systems.

AI Model Support and Toolchain

• Broad model framework support: TensorFlow, TensorFlow Lite, ONNX and OpenVINO.
• Quantization and conversion tools included for converting FP32 models to INT8 and preparing models for the VectorBlox runtime.
• Compilation tools generate binaries and weights; runtime assets are stored in nonvolatile memory (typically SPI Flash) and loaded into DDR at power-up for execution.

CoreVectorBlox IP and Architecture
CoreVectorBlox IP provides a configurable accelerator architecture with features such as:

• Multiple size configurations to match application/performance requirements.
• Overlay architecture to support multiple networks on a single core with dynamic switching.
• Configurable AXI4 memory master interface (64-bit to 256-bit) and AXI4-Lite for control/status.
• Memory-based architecture with memory-mapped input/output support.
• Internal vector processor for general neural networks and a dedicated CNN accelerator for convolutional layers.

Reference Design and Video Pipeline
The PolarFire SoC reference design for evaluation integrates camera and video pipelines including MIPI CSI-2 camera input, HDMI input, an Image Signal Processing (ISP) pipeline, the VectorBlox AI engine and HDMI output for result display. The SDK supports fast prototyping using pre-optimized CNNs and simulation tools for evaluation before deployment.

Power and Edge Deployment
The solution is targeted at low-power edge/embedded applications, with power-efficient inference and video pipelines reported at under 5W in evaluated configurations. Configurability enables balancing throughput and energy consumption for specific use cases.

Getting Started (high level)

• Step 1: Install the VectorBlox™ SDK and consult the Programmer's Guide and included documentation.
• Step 2: Convert and quantize your CNN using the provided tutorial/conversion tools to prepare INT8 models for the SDK.
• Step 3: Evaluate using the PolarFire SoC Video Kit (reference design available) to validate camera/ISP/AI pipelines on target hardware.
• Step 4: Install the Libero® SoC Design Suite to view or rebuild reference design components.
• Step 5: Generate and merge required Libero and CoreVectorBlox licenses per the Libero quick-start guidance before final hardware builds.

Demo and Deployment Flow
The development flow includes trained-model preparation (quantization and compression), compilation to VectorBlox binaries and weights, storing assets in SPI Flash, and loading into DDR memory at runtime. The SDK supports sparse-aware mappings to directly exploit network sparsity in FPGA hardware for improved throughput.

Caractéristiques / spécifications techniques

• Supported devices: PolarFire® FPGAs and PolarFire SoC FPGAs.
• Supported AI frameworks: TensorFlow, TensorFlow Lite, ONNX, OpenVINO.
• Quantization: FP32 -> INT8 conversion tools provided.
• Compression: Structured and unstructured compression for weights/activations/feature maps; sparse storage of nonzero values and indices.
• Interfaces: MIPI CSI-2 (camera), HDMI input/output, SPI Flash for nonvolatile storage, DDR for runtime data.
• Bus/Control: Configurable AXI4 master (64–256 bit) and AXI4-Lite control interface.
• IP features: Overlay architecture, internal vector processor, CNN accelerator.
• Typical evaluated power: inference and video pipelines < 5 W (config-dependent).
• Reference hardware: PolarFire SoC Video Kit (reference design available for camera/ISP/AI pipeline evaluation).
• Required design tool: Libero SoC Design Suite to rebuild or inspect reference design components; license merging steps required per Libero quick-start guidance.