PCI Express Fpga card 100996A1

This product is the optional add on companion board of the PCIed, PCIem, PCIe boards. This is recommended in those cases where a local CPU (e.g. NIOSII core) is required for improving system performances, such as interrupt response time or dedicated pre-processing. The NIOSII processor is able to run up to 200MHz clock frequency, using user defined instructions allowing the user to achieve very high performances in dedicated applications. Furthermore, multiple NIOS (up to 4 cores) can be instantiated on the FPGA. To reduce the number of Fpga I/O pins required to allow the use of the GEB Enterprises FPGA boards J2, the SRAM board has been designed with a partial multiplexed Address/Data Interface. To help the customer to use it on her designs GEB Enterprise has been make available a parametric MSRAM controller IP can be used to interface the SRAM module to the Avalon bus. It contains the logic needed to split the Avalon bus 32 bits cycle in one send address cycle (when its needed) and two data cycles. The MSRAM IP is able to tailor the bus cycle timing to the bus speed during compilation.