Design software HDL Verifier™

verificationFPGA

Verify VHDL and Verilog using HDL simulators and FPGA-in-the-loop test benchesHDL Verifier™ automatically generates test benches for Verilog® and VHDL® design verification. You can use MATLAB® or Simulink® to directly stimulate your design and then analyze its response using HDL cosimulation or FPGA-in-the-loop with Xilinx® and Intel® FPGA boards. This approach eliminates the need to author standalone Verilog or VHDL test benches.HDL Verifier also generates components that reuse MATLAB and Simulink models natively in simulators from Cadence®, Mentor Graphics®, and Synopsys®. These components can be used as verification checker models or as stimuli in more complex test-bench environments such as those that use the Universal Verification Methodology (UVM)