DRAMs

P. 24
define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION

P. 23
Ranked x8 (planar) unbuffered non-ECC ?DDR3 DRAM Device Technology Standard 1-Gb, 2-Gb, and 4-Gb technologies and addressing are supported for x16 and x8 devices. There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module

P. 14
* Access to internal DRAM requires Tsysclk*100 (ns) in a worst case. As for the others accesses, it takes 3 cycles of the internal system clock.

P. 44
25 2.5 2.75 V VDD 1.8 Supply voltage for DRAM interface 1.70 1.8 1.9 V VDD RTC RTC supply voltage 1.3 1.5 1.8 V TC Case temperature -40 85 °C Table 17. Overshoot and undershoot specifications Parameter

P. 29
was specifically developed for the test of SDRAM and DRAM interfaces. The module is based on GOEPEL electronic?s custom CION? ASIC ICs. It enables extended JTAG/Boundary Scan test coverage for all pins including Power and Ground