Analysis software Vista™ Flow

modelingdesigncreation

The Vista Flow consists of the steps typically used by SoC architects, hardware engineers, and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance, and power and integrate with the software. Prototyping, debugging, and analyzing complex systems ESL design methodology allows engineers to perform design optimizations on today's advanced designs more quickly, efficiently, and cost-effectively by prototyping, debugging, and analyzing complex systems before the RTL stage. ESL and RTL methodology leads to a continuation of the design cycle. Quickly explore complex micro-architecture alternatives Vista Model Builder automates the functionality modeling with a set of TLM classes and convenience layer for more efficient and guided behavioral modeling. A TLM code skeleton is automatically derived/generated from a set of ports, registers, and memory declarations, generating compact SystemC source code compliant with TLM 2.0, so users can then model the internal behavior only on their own. Vista Architect Environment Vista Architect offers a set of fast generic models for initial platform assembly and early validation. All models are TLM 2.0 compliant and can be instantiated as building blocks through a text-based format or a block diagram format for assembling any target platform.