Signal integrity tester Summit™ Z74

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Overview
The Summit Z74 is a PCIe 7.0 protocol exerciser designed for validation, debug and compliance development of PCIe and NVMe devices. It provides controlled traffic generation, error injection and link training management for devices operating at data rates up to 128 GT/s. When combined with a Summit M616 analyzer, it enables comprehensive protocol analysis for advanced PCIe testing.

Key capabilities

• Support for PCI Express Specification 7.0 and NVMe traffic generation.
• Traffic generation and protocol stimulation at data rates up to 128 GT/s and link widths up to x4.
• Detailed control of LTSSM transitions for exercising and troubleshooting link states (detect through L0).
• Powerful scripting language for creation of TLPs and DLLPs at PCIe 7.0 rates.
• User-controlled flow control and ACK/NAK policies.
• Emulation of detect-to-L0 LTSSM states, ability to maintain L0 and emulate endpoints, bridges and switches configuration space.
• Lane-level controls: lane reversal, polarity and scrambling configuration.
• Support for dynamic equalization with options to skip EQ phases; error injection during training, per-packet and per-lane.
• Programmed traffic generation and controlled error injection; run test scripts derived from captured traces to validate error recovery.
• Integration with Summit M616 series analyzers to enable full protocol analysis.

PCIe 7.0 Speeds
Supported data rates: 2.5, 5, 8, 16, 32, 64 and 128 GT/s. Link widths supported from x1 to x4. The exerciser can generate test cases to exercise auto-negotiation across these rates.

Resources

• Testing PCI Express L0p Low Power State Using Teledyne LeCroy Protocol Analysis and Exerciser Tools | White Paper
• Summit Z74 Datasheet | Datasheet

Technical specifications

• Model name: Summit Z74
• Technology: PCIe 7.0, NVMe traffic generation
• Maximum data rate: up to 128 GT/s
• Supported data rates: 2.5, 5, 8, 16, 32, 64, 128 GT/s
• Link widths supported: x1 to x4
• LTSSM control: full exercise of LTSSM states (Detect through L0)
• Scripting: creation of TLPs and DLLPs at PCIe 7.0 data rates
• Error injection: training sequences, Data Link and Transaction Layer, per-packet and per-lane
• Lane features: lane reversal, polarity control, scrambling control
• Equalization: supports dynamic equalization and option to skip EQ phases
• Packet automation: automatic generation of packet numbering and CRC where not specified by user
• Configuration space emulation: endpoints, bridges, switches
• Interoperability: use captured trace files as basis for scripted tests with introduced errors
• Analyzer integration: designed to be used with Summit M616 series analyzers for full protocol analysis