CMOS logic gate 74AUP, 74LVC series

standard

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G34 is a dual buffer gate with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. Features and Benefits Advanced Ultra Low Power (AUP) CMOS Supply Voltage Range from 0.8V to 3.6V ±4mA Output Drive at 3.0V Low Static power consumption ICC < 0.9μA Low Dynamic Power Consumption CPD = 6pF Typical at 3.6V Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The hysteresis is typically 250mV at VCC = 3.0V IOFF Supports Partial-Power-Down Mode Operation ESD Protection per JESD 22 Exceeds 200-V Machine Model (A115-A) Exceeds 2000-V Human Body Model (A114-A) Exceeds 1000-V Charged Device Model (C101C) Latch-Up Exceeds 100mA per JESD 78, Class II Leadless packages per JESD30E DFN1410 denoted as X2-DFN1410-6 DFN1010 denoted as X2-DFN1010-6 DFN0910 denoted as X2-DFN0910-6 Totally Lead-Free & Fully RoHS Compliant Halogen and Antimony Free. Green Device