Simulation software HyperLynx

PCB designdesignmodeling

Overview HyperLynx is an integrated analysis and verification software suite for PCB design that supports schematic exploration, pre‑layout simulation, post‑layout verification and 2D/2.5D/3D electromagnetic modeling. It combines SI, PI, EM and DRC capabilities to enable progressive verification workflows and automated optimization.

Main capabilities

• Pre‑layout exploration and constraint definition to set manufacturable rules and stackup choices
• Signal integrity (SI) analysis for general signals, SerDes and DDR interfaces with protocol‑aware checks
• Power integrity (PI) analysis including DC drop, AC/decoupling and PDN transient evaluation
• 2D/2.5D/3D electromagnetic modeling with full‑wave and hybrid solvers for high‑fidelity EM analysis
• Automated design rule checking (DRC) and post‑layout topology extraction for large designs
• Analog/mixed‑signal (AMS) SPICE‑based simulation and multi‑domain coupling
• Automated optimizers: parameter sweeps, expert‑guided exploration and response‑surface techniques

Product family / Applications

• HyperLynx Signal Integrity (HL‑SI)
• HyperLynx Power Integrity (HL‑PI)
• HyperLynx Advanced Solvers (3D EM)
• HyperLynx Design Rule Check (HL‑DRC)
• HyperLynx Analog/Mixed‑Signal (HL‑AMS)
• HyperLynx Schematic Analysis (HL‑SA)
• Z‑Planner Enterprise (stackup planning & materials)

Key features

• Integrated SI/PI/EM/DRC environment with seamless data transfer from schematic to layout
• Progressive verification workflow: fast rule checks followed by higher‑fidelity simulations
• Protocol‑aware compliance and vendor‑specific link analysis for DDR and SerDes
• Batch and automated workflows for large multi‑channel designs
• Scalable for novice to expert users with proven default workflows and advanced solver options

Typical use cases

• Early schematic verification to detect wiring and connectivity errors
• Pre‑layout simulation and stackup planning to define manufacturable constraints
• Post‑layout signoff for SI/PI/EMC and compliance on large multi‑channel boards
• Automated serial‑link analysis with pass/fail reporting and margin quantification
• PDN optimization and decoupling network tuning for transient current demands

Technical specifications

• Supported analyses: SI (time/frequency), PI (DC/AC/transient), AMS (SPICE), 2D/2.5D/3D EM
• Protocol coverage: support for DDRx families and 250+ serial protocol variants
• Optimization: parameter sweeps, expert rules, response‑surface methods
• Workflow integration: schematic → layout → verification, automatic topology extraction
• Stackup planning: Z‑Planner Enterprise with materials library, copper roughness and loss modeling