SoC system-on-chip AM625

Product summary
The AM625 is a human‑machine‑interaction System on Chip (SoC) in the AM62x Sitara™ family. It features scalable Arm® Cortex®‑A53 CPU configurations with embedded edge‑AI capabilities, dual full‑HD display support, 3D graphics acceleration and an extensive set of peripherals targeted at industrial and automotive HMI, gateway and multimedia applications.

Key parameters

• CPU options: 1 / 2 / 4 × Arm Cortex‑A53 up to 1.4 GHz.
• Frequency (MHz): 1400.
• Coprocessors: 1 × Arm Cortex‑M4F (up to 400 MHz).
• Graphics acceleration: 3D GPU; OpenGL ES 3.1, Vulkan 1.2.
• Display type: MIPI DPI, OLDI; dual Full‑HD support.
• Protocols: Ethernet, TSN, IEEE1588.
• Hardware accelerators: CPU; Programmable Real‑Time Unit (PRU) subsystem.
• Operating systems: Android, Linux.
• Security: Secure boot, TEE, HSM.
• Operating temperature range: −40 °C to +125 °C.
• Edge AI enabled: Yes.

Processor cores and caches

• Up to quad 64‑bit Arm Cortex‑A53 microprocessor subsystem at up to 1.4 GHz with 512 KB L2 shared SECDED ECC cache (quad configuration).
• Each Cortex‑A53 core: 32 KB L1 DCache (SECDED ECC) and 32 KB L1 ICache (parity).
• Single‑core Arm Cortex‑M4F MCU up to 400 MHz for real‑time and safety tasks with 256 KB SRAM (SECDED ECC).
• Dedicated Device/Power Manager for low‑power control and domain isolation.

Multimedia and graphics

• Display subsystem: dual‑display support, each up to 1920×1080 @60 fps (examples: 1×2048×1080 + 1×1280×720).
• Pixel clock up to 165 MHz with independent PLL per display; supports OLDI (4‑lane LVDS ×2) and DPI (24‑bit RGB LVCMOS).
• Display safety features: freeze‑frame detection and MISR data check.
• 3D GPU: ≥1 pixel per clock; fillrate >500 Mpixels/s, >500 MTexels/s, >8 GFLOPs; supports ≥2 composition layers and formats ARGB32, RGB565, YUV; OpenGL ES 3.1 and Vulkan 1.2 supported. 2D graphics capable.
• MIPI CSI‑2 camera receiver (4‑lane D‑PHY) supporting 1–4 lanes, up to 1.5 Gbps per lane, virtual channels and DMA to DDR.

Memory subsystem

• On‑chip RAM up to 816 KB composed of multiple banks (OCSRAM 64 KB SECDED ECC, SMS partitions, M4F SRAM, Device/Power Manager RAM).
• DDR subsystem: LPDDR4 and DDR4 support; 16‑bit data bus with inline ECC; up to 1600 MT/s; max addressable: 8 GB (DDR4), 4 GB (LPDDR4).

Security

• Secure boot with hardware‑enforced Root‑of‑Trust; support for backup RoT key switching, takeover protection and anti‑rollback.
• Trusted Execution Environment (TEE) based on Arm TrustZone; extensive firewall/isolation features.
• Dedicated Security Controller with programmable HSM core and security DMA/IPC subsystem.
• Cryptographic acceleration: AES (128/192/256), SHA2 series, DRBG with TRNG, PKA for RSA/ECC, session‑aware crypto engine.
• Secure software‑controlled debug access and security‑aware debugging features.

PRU and real‑time

• Dual‑core Programmable Real‑Time Unit Subsystem (PRUSS) up to 333 MHz for cycle‑accurate GPIO and custom real‑time protocols (UART, I2C, external ADC, etc.).
• PRU memory: 16 KB program memory per PRU (SECDED ECC), 8 KB data memory per PRU (SECDED ECC), 32 KB general‑purpose memory with SECDED ECC; CRC HW accelerator and industrial timers/interrupt controller.

High‑speed interfaces and connectivity

• Integrated Ethernet switch (3‑port: 1 internal + 2 external) with RMII (10/100) or RGMII (10/100/1000), IEEE1588 support, Clause 45 MDIO, ALE packet classifier, priority‑based flow control and TSN support.
• Two USB 2.0 ports (host, device or dual‑role) with VBUS detection.
• General connectivity: 9× UART, 5× SPI, 6× I2C, 3× McASP audio ports, 3× ePWM, 3× eQEP, 3× eCAP, full GPIO support.
• 3× CAN modules with CAN‑FD support (conforms to CAN 2.0A/B and ISO 11898‑1, up to 8 Mbps).

Media, storage and boot options

• 3× MMC/SD/SDIO (1× 8‑bit eMMC up to HS200; 2× 4‑bit SD/SDIO up to UHS‑I).
• GPMC for parallel host interfaces (NAND, NOR, SRAM) with BCH/Hamming ECC and Error Locator Module (ELM).
• OSPI/QSPI with DDR/SDR support, XIP mode with optional on‑the‑fly encryption; supports serial NOR/NAND and up to 4 GB address support.
• Boot options: UART, I2C EEPROM, OSPI/QSPI Flash, GPMC NOR/NAND, Serial NAND, SD Card, eMMC, USB host/device, Ethernet.

Power management

• Device/Power Manager supports low‑power modes: Partial IO wakeup (CAN/GPIO/UART), DeepSleep, MCU‑only modes, Standby and dynamic frequency scaling for Cortex‑A53.
• Recommended companion PMIC: TPS65219.

Functional safety and qualification

• Designed for functional‑safety applications (targeting ISO 26262 system capability up to ASIL D; hardware integrity up to ASIL B; safety documentation and certification plans such as TÜV SÜD indicated).
• AEC‑Q100 qualified.

Technology & packaging

• 16 nm process technology.
• Package options: 13 mm × 13 mm, 0.5 mm pitch, 425‑pin FCCSP BGA (ALW) and 17.2 mm × 17.2 mm, 0.8 mm pitch, 441‑pin FCBGA (AMC).

Additional notes

• AM62x family positioning: cost‑optimized Sitara™ MPUs for Linux application development with scalable Cortex‑A53 performance, dual displays and GPU acceleration for HMI and industrial/automotive applications.
• Includes tools and documentation: datasheet, technical reference manual, errata and application notes, board design and power guides to assist design and deployment.

Technical specifications

• Product name: AM625
• Brand: Texas Instruments
• CPU options: 1 / 2 / 4 × Arm Cortex‑A53 up to 1.4 GHz
• MCU coprocessor: 1 × Arm Cortex‑M4F up to 400 MHz (256 KB SRAM)
• GPU: 3D GPU, OpenGL ES 3.1, Vulkan 1.2, >500 Mpixels/s fillrate
• Displays: Dual Full‑HD (1920×1080 @60fps), MIPI DPI, OLDI
• Ethernet: Integrated 3‑port switch, TSN capable, RGMII/RMII, IEEE1588
• Memory: LPDDR4/DDR4 support up to 1600 MT/s; on‑chip RAM up to 816 KB
• Security: Secure boot, HSM, AES/SHA2/PKA, TRNG, TEE support
• PRU: Dual PRU Subsystem up to 333 MHz
• High‑speed I/O: 2× USB2.0, 9× UART, 5× SPI, 6× I2C, McASP×3, CAN‑FD×3, GPMC, OSPI/QSPI
• Operating temperature: −40 °C to +125 °C
• Power solution: TPS65219 recommended
• Process / package: 16 nm; 13×13 mm FCCSP (425 pin ALW) and 17.2×17.2 mm FCBGA (441 pin AMC)