Clock comparators

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New Products Supplement national.com 2010 Vol. 1 Data Conversion Interface Power Management Clock and Timing Amplifiers and Comparators Audio Automotive and Space Grade

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and WATCHDOG Comparators INT / RST OS BTI INT_IN GPO 10-bit Sigma-Delta ADC Interrupt Masking and Interrupt Control Fan Speed Counter Interface and Control LM96080 Typical Application Circuit ADC12D1x00 ? 12-Bit, 2.0/3.2/3.6 GSPS Ultra-High-Speed ADCs National?s new ADC12D1x00 family

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national.com 13 LMH1983 Crosspoint Switch PLL1 Ref Fbk 27.0 MHz PLL3 3G, HD/1.001 PLL4 Audio Clock CLKout4 CLKout3 CLKout2 CLKout1 93.304 MHz PLL2 3G, HD Genlock PLL LMH1983 ? Multi-Rate Audio/Video Clock Generator Features ? Replaces expensive external 74 MHz/148 MHz VCXOs

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6 DS92LX1621/22 and DS92LX2121/22 ? 16-Bit and 21-Bit, 10 to 50 MHz Channel Link III Embedded Clock Ser/Des with Integrated Zero-Latency, Bidirectional Control Channel Features ? Supports up to 900 Mbps application data payload ? Wide operating range?16-bit parallel data (LVCMOS), 10 to 50

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1000/600/800 E Ultra-high-speed ADC 4 ADC128D818 E 12-bit, 8-channel ADC system monitor with internal/external reference 4 LM96080 E 10-bit, 7-channel system monitor with fan monitoring 5 Interface DS92LV0421/22 24-bit Channel Link II serializer and deserializer with embedded clock 6 DS92LV2421

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counter bits = hex 05 (bin 000101), (number of PWM pulses) - bits [3:0] (comparator value = 2). (length of PWM pulse) Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops. The same example with SelIntFull=0 (limited bit compare) will produce an unlimited number

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.0V check) - Busy flag during measure - Interrupt generated if SVLD measurement low .. 10-Bit Universal Counter - 10, 8, 6 or 4 bit up/down counting - Parallel load - Event counting (PA[1] or PA[3/4]) - 8 different input clocks - Full 10 bit or limited (8, 6, 4 bit) compare function - 2

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S debouncerYesPA[3/4] EdgeFallingPA[3/4] WakeUp on change In Out WakeUp on change In Out RdRegPA 0 PA[3:0] RdRegPA 1 PA[5:4] irqPA[0l/5h] irqPA[3l/4h] WUchEnPA[0/5] WUchEnPA[3/4] InResAH Qdeb Q QB Qdeb Q QB Input to peripherals is blocked if used for SVLD comparator input

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are selected we call that limited bit counting. The counter works in up- or down count mode. Eight clocks can be used as the input clock source, six of them are prescaler frequencies and two are coming from the input pads PA[1] (direct only) and PA[3/4] (direct or debounced). In this case the counter can be

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R EM6580 Copyright © 2007, EM Microelectronic-Marin SA 03/07, rev. J 28 www.emmicroelectronic.com 8.3 Event Counting The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[1] (only non-debounced and only rising edge) or PA[3/4] input

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synthesizer uses lowjitter timing reference clock as time phase reference the internai voltage controlled oscillator vco the phase comparator compares the fractionaln divided clock the original timing reference generates control signal the control signal is filtered the internai loop filter to generale

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synthesizer see hybrid analogdtgital pll page 13 the digrtal pllfirst compares the clkjn frequency to the pll output the fractional n logic block then translates the desired ratio based off clkjn to one based off the internai limmg reference clock sysclk this allows the lowjitter timing reference clock to be

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cirrus logc cs2000cp fractionaln clock synthesizer clock multiplier b features b b general description b the cs2000cp is an extremely versatile b system b b b clocking device that utilizes programmable phase lock loop the cs2000cp is based hybrid analogdigital pll architecture comprised unique

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the evaluation kit b b most calculators do not interpret the fixed point binary representation which the cs2000 uses to define the output to input clock ratio see section 53 1 page 19 however simple conversion we can use these tools to generale binary hex value which can be written to the b b rations b b b b

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b cs2000cp b b 5 applications b b 51 timing reference clock input b the low jitter timing reference clock refclk can be provided either an external reference clock an external crystal conjunction the internal oscillator order to maintain stable lowjitter pll output the timing reference clock must

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-Power Comparators High-Speed Comparators Analog Video Products Sync Separators Clock Generators Crosspoint Switches Analog Multiplexers Amplifiers/Buffers

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LMH6515/ 17 35 ADC ADC12C080, ADC14C105, ADC12DS105, ADC14DS105, ADC16V130, ADC16DV160 22 Clock source LMK01xxx 60 PLL/VCO LMX2531 63 JFET FPGA Clock Distribution System Input Memory + - Rs1 Rs2 Comparator-based Trigger Circuit LMX2531 Input Amplifier + Gain Control + Bandwidth

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Analog Temperature Sensor Conversion Circuit ADC Counter Data Register (RAM) Control Circuit Comparator Circuit PWM Output Controller Limit Register (RAM) 2-Wire Serial Interface Reset Pin GPI/O Pin External Interrupt I/O Fan Speed Control Data I/O Clock Input Digital

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.......................................................................49 Comparators ........................................................................................................50 RF Power Detectors..............................................................................................51 Temperature Sensors Temperature Sensors Product Portfolio

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78 Triple-Rate SDI Development Platform for Xilinx FPGAs In collaboration with Avnet and Xilinx, National Semiconductor developed a triple-rate SDI and video clocking daughter card for the Xilinx Spartan-3A/3E development kits. The daughter card plugs directly into the Spartan development

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up down selectable retentive yes time switches rtc 16 weekly analog comparators 12 0 compare counters 16 soft text messages 16 priority driven auxiliary holding relays 32 b processing characteristics b cycle time msec 100 all special function blocks retentive timers response time msec 85 cycle time backup duration

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functions including 16 timers 16 retentive selectable 4 digit up down counters 16 time switches 16 compare counters 16 soft text messages 32 auxiliary relays 12 analog comparators ability to add up to three 3 expansion modules expanding i o to 32 digital inputs 16 relay outputs 35mm din rail mounting fast