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32-bit microcontroller SAMV71Q21RT series
communicationfor motor controlPWM

32-bit microcontroller - SAMV71Q21RT series - Atmel - communication / for motor control / PWM
32-bit microcontroller - SAMV71Q21RT series - Atmel - communication / for motor control / PWM
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Characteristics

Type
32-bit
Applications
communication, for motor control
Other characteristics
PWM, ADC, analog, pulse width modulation, mixed-signal, low-power, DSP, ARM

Description

Overview
The SAMV71Q21RT is a radiation-tolerant, space-qualified 32-bit microcontroller based on an ARM Cortex-M7 core with double-precision FPU. It delivers up to 300 MHz performance, up to 2 Mbytes of embedded Flash and 384 Kbytes of multi-port SRAM with configurable TCM to support deterministic DSP and real-time control functions. The RT variant provides extended temperature grading and ceramic/hermetic package options for aerospace, defense and space applications.

Key Features
  • ARM Cortex-M7 core at up to 300 MHz with single- and double-precision hardware FPU.
  • 2048 KB embedded Flash and 384 KB multi-port SRAM; configurable instruction/data TCM options (up to 2×128 KB).
  • 16 KB I‑cache and 16 KB D‑cache with ECC; MPU with 16 regions.
  • Embedded voltage regulator, POR, BOD and dual watchdogs for robust power management and safety.
  • Low-power modes (Sleep, Wait, Backup) with BRAM backup and typical backup current ≈1.1 μA (RTC enabled).


Peripherals and Interfaces
  • 10/100 Mbps Ethernet MAC (GMAC) with IEEE-1588 PTP, AVB support and dedicated DMA.
  • High-speed USB with integrated PHY (USB HS) and HS USB interface.
  • Dual MCAN controllers with CAN‑FD support and SRAM-based mailboxes.
  • QSPI (XIP) for up to 256 MB external Flash, two SPI controllers and multiple UART/USART interfaces (LIN, ISO7816, IrDA, RS-485).
  • Image Sensor Interface (12-bit ITU-R BT.601/656), MediaLB, SSC (I2S/TDM) and two I2SC controllers.
  • HSMCI (SDIO/e.MMC), advanced timers/PWM for motor control and up to 114 GPIO lines with interrupt, debouncing and on-die series resistors.
  • Two AFEC controllers (up to 12 channels each), one 2‑channel 12‑bit DAC and one analog comparator controller.


Radiation and Space-Grade Additions
  • Single-event latch-up (SEL) threshold: LET > 60 MeV·cm2/mg (measured at +125 °C).
  • Total Ionizing Dose (TID) capability up to 30 krad(Si).
  • Available in ceramic and hermetic package options with extended qualification flow suitable for aerospace/defense/space use (QML-V / QML-Q equivalent).


Packages
  • CQFP144 — 144-lead CQFP, 22 × 22 mm, 0.5 mm pitch.
  • LQFP144 — 144-lead LQFP, 20 × 20 mm, 0.5 mm pitch.


Documentation and Design Resources
Datasheet, application notes on radiation mitigation and space safety, oscillator guidance for radiation-tolerant clocks, user guides and qualification/packaging screening documentation are available to support design-in and qualification for aerospace and defense programs.

Technical specifications
  • CPU: ARM Cortex‑M7, up to 300 MHz.
  • Flash: 2048 KB embedded.
  • RAM: 384 KB multi-port SRAM.
  • FPU: single- and double-precision hardware FPU.
  • TCM: configurable options up to 2 × 128 KB.
  • ICache / DCache: 16 KB each with ECC.
  • ADC: up to 24 channels, 12-bit.
  • DAC: 2-channel 12-bit DAC (1 MSps per channel).
  • QSPI: Quad I/O with XIP (supports up to 256 MB external Flash).
  • I2C (TWIHS): 3 interfaces.
  • CAN: 2 controllers, CAN‑FD capable.
  • Ethernet: 10/100Base-TX GMAC with AVB and IEEE‑1588 support.
  • Supply voltage: 3.0 V to 3.6 V.
  • Temperature range: -55 °C to +125 °C (RT variant).
  • Radiation: SEL LET > 60 MeV·cm2/mg @ +125 °C; TID up to 30 krad(Si).
  • I/O: up to 114 lines.

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