The CAN FD interface based on a modern FPGA based CAN core architecture (esdACC) is able to send and receive ISO conforming CAN-FD (up to 5 Mbit) or CAN 2.0 A/B messages. The CAN-FD bitrate range is validated from 10 kbit/s up to 5 Mbit/s. Wide Choice of Hardware Designs The CAN-PCIe/402-FD is a PC board designed for the PCIe bus that features one or two CAN-FD interfaces according to ISO 11898-2. These versions are also available without electrical isolation. Equipped with up to two CAN-FD interfaces the board is available as low profile versions (CAN-PCIe/402-1-LP-FD and -LP2-FD).
The independent CAN-FD nets according to ISO 11898-1:2015 are driven by the esdACC (esd Advanced CAN Core) implemented in the Altera FPGA. The FPGA supports bus mastering (first-party DMA) to transfer data to the host memory. This results in a reduction of overall latency on servicing I/O transactions in particular at higher data rates and a reduced host CPU load. Due to the usage of MSI (Message Signaled Interrupts) the CAN-PCIe/402-FD can be operated for example in Hypervisor environments. The CAN-PCIe/402-FD provides high resolution hardware timestamps.
Wide Range of Operating System Support and Advanced CAN Diagnostic:
- Drivers and higher layer protocols for Windows®, Linux®, QNX®, RTX, RTX64 and others
- esd Advanced CAN Core (esdACC) technology