Programmable microchip ADC32RF72

2 channelmixed signaldigital

Product summary
The ADC32RF72 is a 16-bit, dual-channel, non-interleaved RF-sampling analog-to-digital converter (ADC) operating up to 1.5 GSPS. It targets very high SNR and ultra-low noise spectral density, delivering −163.7 dBFS/Hz (improvable to −166.2 dBFS/Hz with internal averaging). Buffered analog inputs offer programmable internal termination (50 Ω, 100 Ω, 200 Ω) and a full-power input bandwidth of 1.8 GHz (−3 dB). The device supports selection of one input from IN1/2/3 in addition to IN0.

Digital processing and interfaces

• 192-tap per-channel programmable FIR equalizer for channel equalization
• 12-bit fractional delay filter
• Up to 8 digital down converters (DDCs) supporting decimation factors /2, /3, /5 up to /32768
• 48-bit NCOs with phase-coherent frequency hopping; fast hopping < 1 μs
• JESD204B/C serial interface with maximum lane rate up to 24.75 Gbps

Spectral and noise performance
The ADC provides ultra-low close-in residual phase noise (example: −140 dBc/Hz at 10 kHz offset at 1 GHz) and strong spectral metrics at fIN = 1 GHz, −1 dBFS:

• SNRflat: 72.1 dBFS
• HD2, HD3: 68 dBc
• Non HD2/3 spurious: 93 dBFS

Power, architecture and inputs
The device uses a single-core (non-interleaved) ADC architecture with buffered inputs and a full-scale input of 1.44 Vpp (4.1 dBm). Typical power consumption is 1.5 W per channel at 1.5 GSPS (≈3.1 W total). Aperture jitter is 40 fs and peak-to-peak input voltage range is 1.4 Vpp. Input termination is programmable (50/100/200 Ω).

Technical specifications

• Model: ADC32RF72
• Sample rate (max): 1500 MSPS
• Resolution: 16 bits
• Number of input channels: 2 (dual channel)
• Interface type: JESD204B, JESD204C (max lane rate 24.75 Gbps)
• Analog input bandwidth (−3 dB): 1.8 GHz
• Full-scale input: 1.44 Vpp; peak-to-peak range: 1.4 Vpp
• Noise spectral density (NSD): −163.7 dBFS/Hz (can improve to −166.2 dBFS/Hz with averaging)
• SNR: 72.1 dB (typical)
• ENOB: 11.8 bits (typical)
• SFDR: 68 dB (typical)
• Aperture jitter: 40 fs
• Power consumption (typ): 1.5 W per channel @ 1.5 GSPS (≈3100 mW total)
• Operating temperature range: −40 to 105 °C
• Input buffer: Yes
• Programmable input termination: 50 Ω, 100 Ω, 200 Ω

Additional notes
The ADC supports internal averaging modes to lower NSD and targets a code error rate (CER) of 1E-15 errors/sample. The device is rated for extended operating temperatures to support system deployments in demanding environments. Selection of alternate inputs (IN1/2/3) and integrated digital processing simplify front-end equalization and channelization tasks.