Radar transceiver AWR2188

RFfor sensorsmonitoring

Product summary
The AWR2188 is a single-chip FMCW radar transceiver operating in the 76–81 GHz band. Implemented in a low-power 45 nm RFCMOS process, it integrates transmitter, receiver, baseband, PLL and ADCs to deliver an 8TX/8RX monolithic radar front end in a small FCCSP package. The device targets low-power, self-monitored, high-accuracy automotive radar systems and is offered as a complete development platform with reference hardware, software drivers and documentation.

High-level description
AWR2188 uses Launch-on-Package (LoP) technology to enable compact, cascadable sensor configurations. The integrated architecture (TX, RX, baseband, ADC, frequency generation) simplifies implementation of multimode sensors (short, mid, long range) through firmware and programming-model changes.

Key features

• Single-chip FMCW transceiver with integrated PLL, transmitter, receiver, baseband and ADC
• 76–81 GHz operation with up to 4.5 GHz continuous chirp bandwidth
• 8 receive channels and 8 transmit channels (8RX/8TX)
• High-accuracy chirp engine based on Fractional‑N PLL
• Typical TX power 13.5 dBm; RX noise figure ~10 dB
• High linearity (P1dB up to −5 dBm) while maintaining noise figure
• Typical front-end power ~2.8 W (8TX/8RX)
• Minimum chirp idle time 3 µs; maximum chirp slope 266 MHz/µs
• ADC sample rate up to 66.67 MSPS
• Built-in calibration, firmware ROM and self-test for on-board monitoring
• Host interfaces: control via SPI or I2C; data via MIPI D-PHY and CSI-2 v1.2; interrupt reporting
• Functional-safety targeted (documentation for ISO 26262; systematic capability up to ASIL‑D targeted; hardware up to ASIL‑B targeted)
• AEC‑Q100 targeted; cascade option to increase channel count; embedded interference detection
• Power management: integrated LDO network; I/Os support 3.3 V / 1.8 V
• Clocking: supports external 40/50 MHz clock (square/sine) or crystal with load capacitors

Package | Pins | Size
FCCSP (APE) package; 573 pins; package area ≈210 mm²; dimensions approx. 14 mm × 15 mm; 0.5 mm pitch LoP launcher positions.

Platform and hardware
Evaluation module AWR2188EVM available to evaluate cascaded and multi-device configurations, with example reference hardware designs and demonstration setups.

Documentation and tools included with the platform
Datasheet, reference hardware design, software drivers, sample configurations, API guide and user documentation provided as part of the platform to support system integration and validation.

Technical specifications

• Frequency range: 76–81 GHz
• Receivers: 8
• Transmitters: 8
• ADC sampling rate (max): 66.67 MSPS
• Interfaces: MIPI‑CSI2 (data), SPI (control), I2C (control optional)
• TX output power (typ): 13.5 dBm
• RX noise figure (typ): 10 dB
• P1dB linearity: up to −5 dBm
• Power consumption (front-end 8TX/8RX): ~2.8 W
• Minimum chirp idle time: 3 µs
• Maximum chirp slope: 266 MHz/µs
• Operating junction temperature: −40 °C to 140 °C (TX module up to −40 °C to 142 °C)
• Recommended power-supply solution example: LP87745‑Q1
• Package: FCCSP (APE), 14 × 15 mm, 0.5 mm pitch, 573 pins