Multi-function network controller netX 50

multi-protocol2 portdata transmission

Overview
The netX 50 is an integrated network controller designed for industrial communication, supporting fieldbus and Real-Time Ethernet applications. It can operate as a companion chip to a host CPU via an integrated dual-port memory or as a stand‑alone solution with digital I/Os. The device embeds a 32-bit ARM 966E-S CPU (200 MHz) with 112 KB RAM and 64 KB ROM; external memory expansion is possible via the 32-bit memory controller (SDRAM, SRAM, FLASH). Extensive peripherals and serial interfaces (UART, USB, SPI, I²C) plus integrated IO‑Link and CCD controller increase application flexibility.

Highlights

• Flexible high-end network controller with host interface or stand‑alone digital I/O mode
• Two communication channels for Real‑Time Ethernet or fieldbus with integrated PHYs
• Integrated dual‑port memory, extension bus option and triple‑buffer/DMA support for high throughput

Protocols supported

• VARAN Client
• Sercos Slave
• PROFINET IO‑Device
• PROFIBUS DP Slave
• POWERLINK Controlled Node
• Open Modbus/TCP Server
• Open Modbus/TCP Client
• EtherNet/IP Adapter
• EtherCAT Slave
• DeviceNet Slave
• CC‑Link Slave
• CANopen Slave

Order information
Product name | Part number | Brief description
NETX 50 | 2230.000 | Network controller for fieldbus slave and Real‑Time Ethernet slave with memory controller

Technical specifications

• CPU: ARM 966E‑S, 32‑bit, 200 MHz
• Internal memory: 112 KByte RAM, 64 KByte ROM
• Integrated dual‑port memory for host communication and status
• Memory controller: 32‑bit, supports external SDRAM, SRAM, FLASH
• Central data switch with five data paths connecting ARM, communication, host and DMA controllers
• Two configurable communication channels with two‑level controller structure (dedicated ALUs + microcode‑driven logic)
• Integrated Ethernet PHYs (reduces external ethernet circuitry to passive components)
• xMAC (Medium Access Controller) and xPEC (Protocol Execution Controller) for low‑level bus access and packet control
• DMA‑supported block transfers and optional triple buffer logic for conflict‑free data exchange
• Peripherals: UART, USB, SPI, I²C; integrated IO‑Link controller and CCD controller